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NLSF595 Serial (SPI) Tri-Color LED Driver
The NLSF595 is advanced CMOS shift register with open drain outputs fabricated with 0.6 mm silicon gate CMOS technology. This device is used in conjunction with a microcontroller, with only one dedicated line. All pins have Overvoltage Protection that allows voltages above VCC up to 7.0 V to be present on the pins without damage or disruption of operation of the part, regardless of the operating voltage. This device may be used between 2.0 and 5.5 volts, the output driver level may be independent of supply voltage: 0-7.0 volts.
Features http://onsemi.com MARKING DIAGRAMS
16 1 QFN-16 MN SUFFIX CASE 485G SF 595 ALYW (Top View)
* Parallel Outputs are Open Drain Capable of Sinking > 12 mA * * * * * * * * * * * * * * * * *
Output Withstands up to +7.0 Regardless of VCC Standard Serial (SPI) Interface, Data, Clock, Enable (Low) All Inputs CMOS Level Compatible Frees up I/O around a Microcontroller Only One Pin Dedicated to this Device (Latch Enable) Output Enable may be Permanently Pulled Low High Speed Clocking, Fmax > 25 MHz (Shift Clock) Eight Bits Parallel Output Double Buffered Outputs, so Register may Fill without Affecting Output STD CMOS Serial Output, may be used to Cascade more than One Device Each Part Controls Two Tri-Color LEDs Two Devices can Control 5 Tri-Color LEDs Low Leakage: ICC = 2.0 mA (Max) at TA = 25C Latchup Performance Exceeds 100 mA QFN-16/TSSOP-16 Packages ESD Performance: Human Body Model; > 2000 V, Machine Model; > 200 V Functionally Similar to the Popular 74VHC595 Pb-Free Packages are Available
16 16 1 TSSOP-16 DT SUFFIX CASE 948F NLSF 595 ALYW 1
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8
A L Y W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
July, 2005 - Rev. 8
Publication Order Number: NLSF595/D
NLSF595
OE RSK SCLR SCK QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA SI OE RCK SCK SCLR SQH 2D 3 SI 1D 2D 3 QA QB QC QD QE QF QG QH SQH R C/1 EN3 C2 SRG8
Figure 1. Pin Assignment (TSSOP-16)
Figure 2. IEC Logic Symbol
VCC
QC 16
QA
QB 15
14
13
QD
1
12
SI (Serial Data Input) OE
QE
2
NLSF595 MN Package
11
QF
3
(Top View)
10
RCK (Register Clock) SCK (Shift Clock)
QG
4
9
5 QH
6 GND 2
7 SQH
8 SCLR (reset)
Figure 3. Pin Assignment (QFN-16)
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NLSF595
OE
RCK
OVT QA
SI
D SRA R D SRB R D SRC R D SRD R D SRE R D SRF R D SRG R D
Q
D STRA
Q OVT QB
Q
D STRB
Q OVT QC
Q
D STRC
Q OVT QD PARALLEL DATA OUTPUTS QE
Q
D STRD
Q OVT
Q
D STRE
Q OVT QF
Q
D STRF
Q OVT QG
Q
D STRG
Q OVT QH
Q SRH
D STRH
Q
SCK R SCLR
SQH
Figure 4. Expanded Logic Diagram
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NLSF595
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG ILATCHUP qJA Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range Latchup Performance Thermal Resistance, Junction-to-Ambient Above VCC and Below GND at 125C (Note 1) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +7.0 -20 $50 +50 $75 450 -65 to +150 $300 128 Unit V V V mA mA mA mA mW C mA C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V Characteristics Min 2.0 0 0 -55 0 Max 5.5 5.5 VCC 125 50 15 Unit V V V C ns/V
FUNCTION TABLE
Inputs Reset (SCLR) L H H H Serial Input (SI) X D X X Shift Clock (SCK) X L, H, L, H, Reg Clock (RCK) L, H, L, H, X Output Enable (OE) L L L L Shift Register Contents L DSRA; SRNSRN+1 U U Resulting Function Storage Register Contents U U ** SRNSTRN Serial Output (SQH) L SRGSRH U * Parallel Outputs (QA - QH) U U ** SRN
Operation Clear shift register Shift data into shift register Registers remains unchanged Transfer shift register contents to storage register Storage register remains unchanged Enable parallel outputs Force outputs into high impedance state
X X X
X X X
X X X
L, H, X X
L L H = High-to-Low = Low-to-High
* * *
U ** **
* * *
U Enabled Z
SR = shift register contents STR = storage register contents
D = data (L, H) logic level U = remains unchanged
* = depends on Reset and Shift Clock inputs ** = depends on Register Clock input
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DC ELECTRICAL CHARACTERISTICS
Symbol VOL2 ILKG IOFF VOH VOL VIH ICC IOZ VIL IIN Power Off Output Leakage All Outputs Active (2) State Off Output Leakage Current QA-QH Three-State Output Off-State Current QA-QH Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage with Max. Load VIN = VIH or VIL Maximum Low-Level Output Voltage VIN = VIH or VIL Minimum High-Level Serial Output Only Output Voltage VIN = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter VIN = VIH or VIL VOUT = VCC or GND VIN = VIH or VIL VOUT = VCC or GND VIN = VIH or VIL IOH = -4 mA IOH = -8 mA VIN = 0 or 5.5 V VOUT = 5.5 V VIN = VCC or GND VIN = 5.5 V or GND IOL = 20 mA IOL = 25 mA IOL = 4 mA IOL = 8 mA IOL = 50 mA VIN = VIH or VIL IOH = - 50 mA Test Conditions
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NLSF595
5 0 to 5.5 VCC (V) 5.5 5.5 5.5 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0 1.5 2.1 3.15 3.85 2.58 3.94 Min 1.9 2.9 4.4 TA = 25C Typ 0.8 0.5 0.0 0.0 0.0 2.0 3.0 4.5 0.25 0.25 0.25 $0.1 0.36 0.36 Max 0.59 0.9 1.35 1.65 4.0 1.0 0.6 0.1 0.1 0.1 TA = 85C 1.5 2.1 3.15 3.85 2.48 3.80 Min 1.9 2.9 4.4 40.0 0.44 0.44 Max 2.5 2.5 2.5 1.0 0.59 0.9 1.35 1.65 1.1 0.7 0.1 0.1 0.1 TA = 125C 1.5 2.1 3.15 3.85 2.34 3.66 Min 1.9 2.9 4.4 $2.5 $2.5 $2.5 $1.0 40.0 1.25 0.8 0.52 0.52 Max 0.59 0.9 1.35 1.65 0.1 0.1 0.1 Unit mA mA mA mA mA V V V V V
NLSF595
II I I II I II I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I II I II IIII I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I III II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII I I II I I I I II I I I I II I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I I I I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol fmax Parameter TA = 25C Typ 150 185 TA = 85C Min 70 TA = 125C Min 70 Max Test Conditions Min 80 Max Max Unit Maximum Clock Frequency (50% Duty Cycle) Propagation Delay, SCK to SQH VCC = 3.3 $ 0.3 V VCC = 5.0 0.5 V VCC = 3.3 $ 0.3 V VCC = 5.0 $ 0.5 V VCC = 3.3 $ 0.3 V VCC = 5.0 $ 0.5 V VCC = 3.3 $ 0.3 V VCC = 5.0 $ 0.5 V MHz ns 135 115 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 115 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 tPLH, tPHL CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 8.8 11.3 6.2 7.7 13.0 16.5 15.0 18.5 9.4 11.4 15.0 18.5 9.4 11.4 8.2 10.2 tPHL Propagation Delay, SCLR to SQH 8.4 10.9 5.9 7.4 12.8 16.3 13.7 17.2 9.1 11.1 13.7 17.2 9.1 11.1 ns 8.0 10.0 tPLZ Output Disable Time RCK to QA-QH Output Enable Time RCK to QA-QH Output Disable Time RCK to QA-QH Output Enable Time RCK to QA-QH 7.7 10.2 5.4 6.9 7.7 10.2 5.4 6.9 7.5 9.0 4.8 8.3 11.9 15.4 7.4 9.4 11.9 15.4 7.4 9.4 11.5 15.0 13.5 17.0 8.5 10.5 13.5 17.0 8.5 10.5 13.5 17.0 10.0 12.0 16.2 11.0 10 10 13.5 17.0 8.5 10.5 13.5 17.0 8.5 10.5 13.5 17.0 10.0 12.0 16.2 11.0 10 10 ns tPZL VCC = 3.3 $ 0.3 V VCC = 5.0 $ 0.5 V ns tPZL Output Enable Time, OE to QA-QH VCC = 3.3 $ 0.3 V RL = 1 kW VCC = 5.0 $ 0.5 V RL = 1 kW VCC = 3.3 $ 0.3 V RL = 1 kW VCC = 5.0 $ 0.5 V RL = 1 kW CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF ns 8.6 10.6 tPLZ Output Disable Time, OE to QA-QH 12.1 7.6 4 6 15.7 10.3 10 ns CIN Input Capacitance pF pF COUT Three-State Output Capacitance (Output in High-Impedance State), QA-QH Typical @ 25C, VCC = 5.0 V 87 CPD Power Dissipation Capacitance (Note 2) pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.8 -0.8 Max 1.0 -1.0 3.5 1.5 Unit V V V V
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I II I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII IIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII III I I IIII II IIIIIIIIIIIIIII I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIII I II
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol tsu(H) tsu(L) tw(L) th(L) trec tsu tw th Pulse Width, SCLR Pulse Width, SCK or RCK Recovery Time, SCLR to SCK Hold Time, SCLR to RCK Hold Time, SI to SCK Setup Time, SCLR to RCK Setup Time, SCK to RCK Setup Time, SI to SCK Parameter
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NLSF595
VCC V
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
7 Typ TA = 25C Limit 5.0 5.0 5.0 5.0 3.0 2.5 1.5 2.0 8.0 5.0 8.0 5.0 3.5 3.0 0 0 TA = - 40 to 85C Limit 5.0 5.0 5.0 5.0 3.0 2.5 1.5 2.0 9.0 5.0 8.5 5.0 3.5 3.0 0 0 TA = - 55 to 125C Limit 5.0 5.0 5.0 5.0 3.0 2.5 1.0 1.0 1.5 2.0 9.0 5.0 8.5 5.0 3.5 3.0 Unit ns ns ns ns ns ns ns ns
NLSF595
2.7 V +5.0 V SCLR OE 2.7 V 220 W Red Green
NLSF595
Blue I/O or SPI (MISO) Data Clock EN SI SCK 5 Additional Outputs RCK SQH
MCU
Serial Data Out
NLSF595
8 Additional Outputs Total of 5 3-Color Displays
QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8 NLSF595DTR2
16 VCC 15 QA 14 SI 13 OE 12 RCK 11 SCK 10 SCLR 9 SQH
Figure 5. NLSF595 Shown Driving 5 3-Color LEDs
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NLSF595
SWITCHING WAVEFORMS
tw SCK 50% tw 1/fmax tPLH SQH 50% VCC tPHL VCC GND SCLR tPHL SQH 50% VCC trec SCK 50% VCC GND 50%
VCC GND
Figure 6.
Figure 7.
RCK
50%
VCC GND tPLZ tPZL 50% VCC
OE
50% tPZL tPLZ
50%
VCC GND HIGH IMPEDANCE VOL +0.3V
QA-QH
50% VCC
VOL +0.3 V
QA-QH
VOL +0.3 V
Figure 8.
VCC VALID SI 50% tsu SCK or RCK th 50% GND VCC GND VCC GND RCK SCK
Figure 9.
SCLR
50%
50% tsu(H) 50% tw
VCC GND VCC GND
Figure 10.
Figure 11.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 12.
Figure 13.
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NLSF595
SCK SI SCLR RCK OE
QA QB QC QD QE QF QG QH SQH NOTE: output is in a high-impedance state.
Figure 14. Timing Diagram
INPUT
Figure 15. Input Equivalent Circuit
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NLSF595
QA ON 0 QB OFF 1 QC OFF 1 QD OFF 1 QE ON 0 QF ON 0 QG OFF 1 QH ON 0 Data must be valid at the time of the positive edge.
LED DATA Data Duty Cycle Not Important Clock
250 ns
See Data Sheet for Pinout +2.5 V QA QB For Cascading Devices Data Clock EN SQH QC QD SI SCK RCK OE QE QF QG QH +5.0 V
Figure 16. NLSF595 Example
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NLSF595
ORDERING INFORMATION
Device Nomenclature Device Order Number NLSF595MNR2 NLSF595MNR2G NLSF595DTR2 Circuit Indicator NL NL NL Technology SF SF SF Device Function 595 595 595 Package Suffix MN MN DT Tape & Reel Suffix R2 R2 R2 Package QFN QFN (Pb-Free) TSSOP* (Pb-Free) Shipping 13-inch/2500 Unit 13-inch/2500 Unit 13-inch/2500 Unit
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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NLSF595
PACKAGE DIMENSIONS
QFN-16 MN SUFFIX CASE 485G-01 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
D
A B
PIN 1 LOCATION
0.15 C 0.15 C TOP VIEW
16X
L
5
NOTE 5 4
16X
K
1 12
16X
b
16 X
0.10 C A B 0.05 C
NOTE 3
CC CC
D2 e
8 9 16 13
E
EXPOSED PAD
DIM A A1 A3 b D D2 E E2 e K L
E2 e 0.10 C (A3) A 0.08 C SIDE VIEW A1 C
SEATING PLANE
BOTTOM VIEW
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
0.575 0.022
EXPOSED PAD
3.25 0.128
1.50 0.059
0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLSF595
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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SECTION N-N
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NLSF595/D

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